LM3S828 Datasheet, PDF (157/526 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S828 Microcontroller
5.2.4.3
5.2.4.4
5.2.4.5
5.2.4.6
Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field (continued)
SYSDIV
Divisor Frequency
(BYPASS=0)
Frequency (BYPASS=1)
StellarisWare Parameter^a
0xB
/12 16.67 MHz
Clock source frequency/12
SYSCTL_SYSDIV_12
0xC
/13 15.38 MHz
Clock source frequency/13
SYSCTL_SYSDIV_13
0xD
/14 14.29 MHz
Clock source frequency/14
SYSCTL_SYSDIV_14
0xE
/15 13.33 MHz
Clock source frequency/15
SYSCTL_SYSDIV_15
0xF
/16 12.5 MHz (default) Clock source frequency/16
SYSCTL_SYSDIV_16
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 170) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software configures the main PLL input reference clock source, specifies the output divisor
to set the system clock frequency, and enables the main PLL to drive the output.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 173). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 170)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC register fields (see page 170).
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is T_READY (see Table
17-7 on page 487). During the relock time, the affected PLL is not usable as a clock reference.
PLL is changed by one of the following:
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