LM3S828 Datasheet, PDF (14/526 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 113
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 115
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 116
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 117
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 118
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 122
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 128
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 129
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 130
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 131
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 132
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 134
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 135
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 135
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 135
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 135
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 137
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 137
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 137
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 137
System Control ............................................................................................................................ 150
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 162
Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 .................................. 164
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 165
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 166
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 167
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 168
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 169
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 170
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 173
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 174
Register 11: Clock Verification Clear (CLKVCLR), offset 0x150 ............................................................ 175
Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ................................. 176
Register 13: Device Identification 1 (DID1), offset 0x004 ..................................................................... 177
Register 14: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 179
Register 15: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 180
Register 16: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 182
Register 17: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 184
Register 18: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 186
Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 187
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 189
Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 191
Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 192
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 194
Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 196
Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 198
Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 199
Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 201
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June 18, 2012
Texas Instruments-Production Data