SMH4804 Datasheet, PDF(5/41 Page) Summit Microelectronics, Inc. – -48V Programmable Hot Swap Sequencing Power Controller

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SMH4804 Datasheet, PDF (5/41 Pages) Summit Microelectronics, Inc. – -48V Programmable Hot Swap Sequencing Power Controller

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SMH4804

Functional Description

VGATE sensor makes sure that the power MOSFET is

operating well into its saturation region before allowing the

loads to be switched on. Once VGATE reaches VDD â VGT

this sensor is latched.

When the external MOSFET is properly switched on the

PG[4:1]# outputs may be enabled. Output PG1# is activated

first, followed by PG2# after a delay of tPGD, PG3# after

another tPGD delay, and PG4# after a final tPGD delay. The

delays built into the SMH4804 allow timed sequencing of

power to the loads. The delay times are programmable from

50Âµs to 160ms using bits 3:2 of Register 3 and bit 3 of

and Register 9 - Address 1001 on page 38 for more

information.

The ENPGA, ENPGB, and ENPGC input pins in Figure 5

are used to enabled the PG[4:1]# outputs. The ENPGA pin

controls the PG[4:2]# outputs. If ENPGA is deasserted by

external logic, the SMH4804 disables the PG[4:2]# outputs

and they enter the high-impedance state. The ENPGA input

must be asserted in order for PG[4:2]# to be driven by the

SMH4804.

The ENPGB pin controls the PG[4:3]# outputs. If ENPGB is

deasserted by external logic, the SMH4804 disables the

PG[4:3]# outputs and they enter the high-impedance state.

The ENPGB input must be asserted in order for PG[4:3]# to

be driven by the SMH4804.

The ENPGC pin controls the PG[4]# output. If ENPGC is

deasserted by external logic, the SMH4804 disables the

PG[4]# outputs and the output enters the high-impedance

state. The ENPGC input must be asserted in order for

PG[4]# to be driven by the SMH4804.

This cascaded control mechanism is useful for enabling

supplies that have dependencies based on the other

voltages in the system.

The PG[4:1] outputs have a 12V withstand capability, so

high voltages must not be connected to these pins. Bipolar

transistors or opto-isolators can be used to boost the

withstand voltage to that of the host supply. Refer to

Figure 18 for connectivity information.

Figure 5 shows the relationship between the PG[4:1]# and

the ENPG[C:A] signals.

PG1#

tPGD

ENPGA

PG2#

tPGD

ENPGB

PG3#

tPGD

ENPGC

PG4#

2050 Fig02 2.1

Figure 4. PG Output and ENPG Input Relationship

Forced Shutdown â Secondary Feedback

The Forced Shutdown signal (FS#) is an active low input

that provides a method of receiving feedback from the

secondary side of the DC/DC controllers. A built-in

shutdown timer allows the SMH4804 to ignore the state of

the FS# input until the timer period expires. The timer period

is defined in bits 2:0 of Register 5. The FS# input must be

driven high by the end of this timer period. A low level on this

input causes a Fault condition, driving the FAULT# pin low

and shutting off the VGATE and PG[4:1]# outputs.

The purpose of the shutdown timer is to allow enough time

for devices on the secondary side of the DC/DC controllers

to power up and stabilize. This feature allows supervisory

circuits such as an SMS44 to control the shutdown of the

primary side soft start circuit, even though the secondary

side initially has no power.

Alternatively, the FS# input can be programmed to act as a

fourth ENPG input controlling the PG1# output. This is

combined with an option to independently enable PG1#

with no affect on the other PG[4:2]# outputs, or it can be

programmed so PG1# is the enabling output for the other

outputs.

Summit Microelectronics

2050 3.7 10/30/02

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