SMH4804 Datasheet, PDF (28/41 Pages) Summit Microelectronics, Inc. – -48V Programmable Hot Swap Sequencing Power Controller

Programming Information
SMH4804
S
T
A
R
R
/
Master _T
W
NS
A
AT
C
CO
K
KP
SDA
1 01 0 x xxRx xx x xx x x x x x x
Slave
A
C
K
2050 Fig13
Figure 23. Read Protocol
During a Master write, the SMH4804 receives eight bits of
data, then generates an Acknowledge signal. It device
continues to generate the ACK condition on SDA until a
Stop condition is generated by the Master. The write
transfer protocol on SDA is shown in Figure 24.
S
T
S
A
R
T
R
/
O
Master _T
W
P
SDA
1 0 1 0 x x xW x x x x x x x x x x x x
Slave
A
A
A
C
C
C
K
K
K
2050 Fig14
Figure 24. Write Protocol
Random Access Read
Random address read operations allow the Master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the Master
issues a Write command which includes the Start condition
and the Slave address field (with the R/W bit set to Write)
followed by the address of the word it is to read. This
procedure sets the internal address counter of the
SMH4804 to the desired address.
After the word address Acknowledge is received by the
Master, it immediately reissues a Start condition followed by
another Slave address field with the R/W bit set to Read.
The SMH4804 responds with an Acknowledge and then
transmits the 8 data bits stored at the addressed location. At
this point, the Master sets the SDA line to NACK and
generates a Stop condition. The SMH4804 discontinues
data transmission and reverts to its standby power mode.
Sequential Reads
Sequential reads can be initiated as either a current address
read or a random access read. The first word is transmitted
as with the other byte Read modes (current address byte
Read or random address byte Read). However, the Master
now responds with an Acknowledge, indicating that it
requires additional data from the SMH4804.
The SMH4804 continues to output data for each
Acknowledge received. The Master sets the SDA line to
NACK and generates a Stop condition. During a sequential
Read operation the internal address counter is
automatically incremented with each Acknowledge signal.
For Read operations all address bits are incremented,
allowing the entire array to be read using a single Read
command. After a count of the last memory address the
address counter rolls over and the memory continues to
output data.
Master
SDA
Slave
S
T
DEVICE
A
R
IDENTIFIER
Typical Write Operation
S
T
O
T
P
10
1
1
AA
21
A
0
R
/
W
AA A A A A A A
76 5 4 3 2 1 0
DDDDDDDD
76543210
A
A
A
BUS
C
ADDRESS ^K
C
K
C
K
S
T
DEVICE
Master
A
R
IDENTIFIER
T
Typical Read Operation
S
T
A
R
T
SDA
10
1
1
AA
21
A
0
R
/
W
AA A A A A A A
76 5 4 3 2 1 0
10
1
1
AA
21
A
0
R
/
W
NS
AT
CO
KP
DDDDDDDD
76543210
Slave
A
BUS
ADDRESS
C
K
A
C
K
A
C
2050 Fig15 3.0
K
Figure 25. Sequential Bus Cycles
28
2050 3.7 10/30/02
Summit Microelectronics