SMH4804 Datasheet, PDF (12/41 Pages) Summit Microelectronics, Inc. – -48V Programmable Hot Swap Sequencing Power Controller

Pin Descriptions
SMH4804
Pin Number Pin Number
(28-Pin SOIC) (48-Pin TQFP)
20
28
21
29
22
30
23
32
24
34
25
36
Pin Type
(I/O)
Pin Name
Description
O
2.5VREF
This is a precision 2.5V output reference voltage that
may be used to expand the logic input functions on the
SMH4804. The output reference voltage is with
respect to V_SS.
I
ENPGC
The active-high ENPGC input controls the PG4#
output. When ENPGC is low, the PG4# output is
immediately placed in a high-impedance state. When
ENPGC is high, or left floating, PG4# is driven low at
a time period of t_PGD after PG3# is asserted. This pin
has an internal 50kΩ pull-up to 5V.
I
ENPGB
The active-high ENPGB input controls the PG3# and
PG4# outputs. When ENPGB is low, the PG3#, and
PG4# outputs are immediately placed in a high-
impedance state. When ENPGB is high, or left
floating, PG3# is driven low at a time period of tPGD
after PG2# is asserted. This pin has an internal 50kΩ
pull-up to 5V.
I
ENPGA
The active-high ENPGA input controls the PG2#,
PG3#, and PG4# outputs. When ENPGA is low, the
PG2#, PG3#, and PG4# outputs are immediately
placed in a high-impedance state. When ENPGA is
high, or left floating, PG2# is driven low at a time
period of tPGD after PG1# is asserted. This pin has an
internal 50kΩ pull-up to 5V.
O
PG3#
The PG3# output is an open-drain, active low signal
with no internal pull-up resistor. This pin can be used
to switch a load or enable a DC/DC converter. PG1#
is enabled immediately after VGATE reaches V_DD -
V_GT and the DRAIN SENSE voltage is less than 2.5V.
Each successive PGn# output (PG2# → PG3# →
PG4#) is enabled t_PGD after its predecessor, provided
that the ENPGx inputs are high. The voltage on this
pin cannot exceed 12V relative to V_SS. ENPGx refers
to the ENPGA, ENPGB, and ENPGC inputs.
O
PG1#
The PG1# output is an open-drain, active low signal
with no internal pull-up resistor. This pin can be used
to switch a load or enable a DC/DC converter. PG1#
is enabled immediately after VGATE reaches V_DD -
V_GT and the DRAIN SENSE voltage is less than 2.5V.
Each successive PGn# output (PG2# → PG3# →
PG4#) is enabled t_PGD after its predecessor, provided
that the ENPGx inputs are high. The voltage on this
pin cannot exceed 12V relative to V_SS. ENPGx refers
to the ENPGA, ENPGB, and ENPGC inputs.
Table 1. SMH4804 Pin Descriptions (Continued)
12
2050 3.7 10/30/02
Summit Microelectronics