SMH4804 Datasheet, PDF (17/41 Pages) Summit Microelectronics, Inc. – -48V Programmable Hot Swap Sequencing Power Controller

SMH4804
I2C 2-Wire Serial Interface AC Operating Characteristics
–
I²C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise notes. All voltages are relative to GND.)
Symbol
f_SCL
t_LOW
t_HIGH
t_BUF
t_SU:STA
t_HD:STA
t_SU:STO
t_AA
t_DH
Parameter
SCL clock frequency
Clock period low
Clock period high
Bus free time¹
Start condition setup time
Start condition hold time
Stop condition setup time
Clock edge to valid output
Data out hold time
t_R
t_F
t_SU:DAT
t_HD:DAT
t_I
t_WR
SCL and SDA rise time¹
SCL and SDA fall time¹
Data in setup time
Data in hold time
Noise filter SCL and SDA¹
Write cycle time
1. Values are guaranteed by the design.
Conditions
Before new transmission
SCL low to valid SDA (cycle n)
SCL low (cycle n+1) to SDA
change
Noise suppression
Min
Max
Units
0
100
kHz
4.7
µs
4.0
µs
4.7
µs
4.7
µs
4.0
µs
4.7
µs
0.2
3.5
µs
0.2
µs
1000
ns
300
ns
250
ns
0
ns
100
ns
5
ms
–
TIMING DIAGRAM
Figure 12 shows a timing diagram for the Bus Interface Memory timing. The table above lists the AC timing
parameters for Figure 12. One bit of data is transferred during each clock pulse. Note that data must remain
stable when the clock is high.
tR
SCL
tSU:SDA
SDA In
SDA Out
tF
tHIGH
tLOW
tHD:SDA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tAA
tDH
Figure 12. Bus Interface Memory Timing
2050 Fig09 2.0
Summit Microelectronics
2050 3.7 10/30/02
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