SMH4804 Datasheet, PDF (29/41 Pages) Summit Microelectronics, Inc. – -48V Programmable Hot Swap Sequencing Power Controller

SMH4804
Programming Information
Register Access
The SMH4804 contains a 2-wire bus interface for register
access as explained in the previous section. This bus is
highly configurable, while maintaining the industry standard
protocol. The SMH4804 responds to one of two selectable
Device Type Addresses: 1010_BIN, generally assigned to NV-
memories, or 1011_BIN, which is the default address for the
SMH4804. The Device Type Address is assigned by
programming bit 3 of Register 8.
Register accesses are also programmable using bits 2:1 of
Register 8. Accesses can be denied (no reads or writes),
read only, or read/write (default state).
The SMH4804 has three address pins, A[2:0], associated
with the 2-wire bus. The SMH4804 can be configured to
respond to:
• only to the proper serial data string of the Device Type
Address and specific bus addresses (Register 8, bit 0
set).
• the Device Type Address and any bus address
(Register 8, bit 0 cleared).
Development Hardware and Software
The end user can use the Summit SMX3200 programming
cable and software to connect the board containing the
SMH4804 to the personal computer. See Figure 26 for
board connections. The programming cable interfaces
directly between a PC’s parallel port and the and the 10-pin
connector shown in Figure 26. The application’s values are
entered via an intuitive graphical user interface employing
drop-down menus.
After the desired settings for the application are determined
the software generates a hex file that can be written to the
SMH4804. This file contains the customer part number and
is used to customize the devices during the final electrical
test operations.
Figure 26 shows a diagram of the SMH4804 programming
connections.
−48V RTN0V(0V)
R_D
Top view of straight 0.1" × 0.1" closed
side connector SMX3200 interface
Pin 10, Reserved
Pin 8, Reserved
Pin 6, Reserved
Pin 4, SDA
Pin 2, SCL
Pin 9, 5V
Pin 7, 10V
Pin5, Reserved
Pin3, GND
Pin 1, GND
VDD _A0
A1
SMH4804 A2
SDA
VSS ^SCL
–48V
10 9
87
65
43
21
C1
0.01µF
2050 Fig08
Figure 26. SMH4804 Programming Connection
Caution: Damage may occur when connecting the dongle to
a system utilizing an earth-connected positive terminal.
Master/Slave Protocol
The master/slave protocol defines any device that sends
data onto the bus as a transmitter and any device that
receives data as a receiver. The device controlling data
transmission is called the Master and the controlled device
is called the Slave. The SMH4804 is always a Slave device,
since it never initiates any data transfers. One data bit is
transferred during each clock pulse. The data on the SDA
line must remain stable during clock high time, because a
change on the data line while SCL is high is interpreted as
either a Start or a Stop condition.
Register Bit Maps
The SMH4804 has eight user programmable, nonvolatile,
configuration registers. Although 8-bit data transfers are
used for reading and writing the registers, only the 4 lease
significant bits of each register are utilized by the device.
Therefore, in each of the following registers, bits 7:4 are left
blank. Bits 3:0 are used as shown for each register.
Summit Microelectronics
2050 3.7 10/30/02
29