SMH4804 Datasheet, PDF (38/41 Pages) Summit Microelectronics, Inc. – -48V Programmable Hot Swap Sequencing Power Controller

Registers
SMH4804
Register 9 - Address 1001
In this register, bit 3 works in conjunction with Register 3, bits 2 and 3. Refer to the Register 3 description for
details. Bit 2 sets UV/OV conditions to be either latched or not latched. Bits 1 and 0 select the delay from the
point where both PD[2:1]# inputs are low (or initial power up conditions) to when sequencing can commence.
Bits
Default R/W
Description
3210
00
1
When bit 3 is cleared, the power good sequence is set to Fast.
0b1 R/W
When bit 3 is set, the power good sequence is set to Slow.
0
When bit 2 is cleared, UV/OV conditions are not latched.
0b0 R/W
1
When bit 2 is set, UV/OV conditions are latched.
00
When bits 1:0 are set to 0b00, the PD delay is 0.5 ms.
01
When bits 1:0 are set to 0b01, the PD delay is 80 ms.
0b01 R/W
10
When bits 1:0 are set to 0b10, the PD delay is 160 ms.
11
When bits 1:0 are set to 0b11, the PD delay is 320 ms.
Table 10. Register 9 Bitmap
Register C - Address 1100
This register is not a configuration register, but rather a nonvolatile fault latch (NVFL). If a circuit breaker fault
condition is detected and the NVFL is enabled (Register 5, Bit 3 cleared), bit 0 of Register C is automatically set
(written with a logic ‘1’) when the circuit breaker trips. So long as the bit remains set, the SMH4804 is not able
to drive VGATE or the PG[4:1]# outputs. The host or service center must access the register and clear the bit
(write a ‘0’) once the fault condition has been resolved. The bit can also be used as a nonvolatile Power on/off
control to power the SMH4804 and system through the I²C bus.
Bits
Default R/W
Description
3210
0
When bit 0 is cleared, the NV fault latch is cleared. This bit is
cleared by software once the fault condition is resolved.
When cleared by an I²C command, the VGATE and PG[4:1]#
outputs will power the system on.
0b0 R/W
1
When bit 0 is set, the NV fault latch is set. This bit is set
automatically by hardware when a fault is detected.
When set by an I²C command, the VGATE and PG[4:1]#
outputs will power the system off.
Table 11. Register 9 Bitmap
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2050 3.7 10/30/02
Summit Microelectronics