SMH4804 Datasheet, PDF (32/41 Pages) Summit Microelectronics, Inc. – -48V Programmable Hot Swap Sequencing Power Controller

Registers
SMH4804
Register 3 - Address 0011
This register is used to control the sequencing delays from PG1# to PG2#, PG2# to PG3#, and PG3# to PG4#.
The SMH4804 provides two levels of sequencing delay: fast and slow, which is selected by programming bit 3
of Register 9. These two bits are effectively concatenated with R9 bit 3, providing 8 programmable delay periods.
Refer to Register 9 for more information.
NOTE - Bit 1 controls the effect of the MODE pin. When set (high) the pin functions as described in the pin
descriptions. If the bit is cleared (low) the state of the pin is ignored and the circuit breaker enters latch mode.
Bit 0 enables or disables the function of the PD[4:1]# inputs
Bits
Default R/W
Description
3210
Register 9, bit 3 = 0
00
PG[4:1]# Sequencing delay: 1500 µs.
01
10
0b00
PG[4:1]# Sequencing delay: 50 µs.
R/W
PG[4:1]# Sequencing delay: 250 µs.
11
PG[4:1]# Sequencing delay: 500 µs.
Register 9, bit 3 = 1
00
PG[4:1]# Sequencing delay: 5 ms.
01
10
0b00
PG[4:1]# Sequencing delay: 20 ms.
R/W
PG[4:1]# Sequencing delay: 80 ms.
11
PG[4:1]# Sequencing delay: 160 ms.
Register 9, bit 3 = 1 or 0
0
When bit 1 is cleared (0), the CB MODE MODE is disabled
(see NOTE above).
0b1
1
R/W _{When bit 1 is set (1), the CB MODE is enabled (see NOTE}
above).
0
0b0
1
When bit 0 is cleared, the PD1# and PD2# signals are
disabled.
When bit 0 is set, the PD1# and PD2# signals are enabled.
Table 4. Register 3 Bitmap
32
2050 3.7 10/30/02
Summit Microelectronics