SMH4804 Datasheet, PDF (34/41 Pages) Summit Microelectronics, Inc. – -48V Programmable Hot Swap Sequencing Power Controller

Registers
SMH4804
Register 5 - Address 0101
Register 5 controls the function of the nonvolatile fault latch and provides general control for the FS# input. Bit
3 controls the enabling of the non-volatile latch. Bits 2:0 configure the FS# input.
The FS# pin has two basic functions: it can be programmed to act as an auxiliary enable input controlling the
PG1# output, or it can be programmed to be an event monitor during the power-up sequence.
These bits also control the interrelationship of the PG[4:1]# outputs. In a cascade operating mode PG1# must
be true before PG2# can be true, etc. This interrelationship can be disabled so that each PG[4:1]# output is
effectively controlled by its corresponding ENGPx# input, as long as the primary supply, VGATE and DRAIN
SENSE pins are within their operating limits.
When programmed as an enable to PG1# there are two options: 010_BIN disables the cascade mode (the
PG[4:1]# outputs can act independently) and FS# effectively becomes the enable input for PG1#; 011_BIN
enables the cascade mode and makes FS# the enable input for PG1#. In this mode, PG1# must be active before
PG2# can be activated, followed by PG3#, then PG4#.
The event monitor mode is generally implemented in conjunction with a monitoring device on the secondary side
of the DC/DC converters, such as the SMS44, SMT4004 or SMS64. If FS# is not pulled high before the
programmed condition then the PG[4:1]# and VGATE outputs are shut down. As an example, if the binary value
is 111_BIN, VGATE and PG1# are shut down if FS# is not pulled high before t_PGD has elapsed after PG1# is true.
None of the other PG[4:1]# outputs are activated. If a failure occurs due to the lapse of the event monitor timer,
cycling the power resets the device.
Bits
Default R/W
Description
3210
0
When bit 3 is cleared, the non-volatile latch is enabled.
0b1 R/W
1
When bit 3 is set, the non-volatile latch is disabled.
000
When bits 2:0 are 0b000, the FS function: PG4 + t_PGD cascade
is disabled for simultaneous assertion of the PG[4:1]# pins.
001
When bits 2:0 are 0b001, the FS function is disabled (=1).
010
When bits 2:0 are 0b010, the FS function is active (=1) before
PG1 enabled. Cascade disabled for simultaneous assertion of
the PG[4:1]# pins.
0 1 1 ^{0b100 R/W} When bits 2:0 are 0b011, the FS function must be high (de-
asserted) before PG1 is enabled.
100
101
110
111
FS function: PG4 + t_PGD (PG Delay)
FS function: PG3 + t_PGD (PG Delay)
FS function: PG2 + t_PGD (PG Delay)
FS function: PG1 + t_PGD (PG Delay)
Table 6. Register 5 Bitmap
34
2050 3.7 10/30/02
Summit Microelectronics