SMH4804 Datasheet, PDF (33/41 Pages) Summit Microelectronics, Inc. – -48V Programmable Hot Swap Sequencing Power Controller

SMH4804
Registers
Register 4 - Address 0100
Register 4 enables PG[4:1]# signal sequencing, sets the O/U voltage filter timing, and selects the circuit breaker
cycle time.
Bit 3 of this register enables or disables the PG[4:1]# sequence delays. When set, the delays are defined in
registers 3 and 9. If bit 3 is cleared, no delay is incurred and sequencing is based solely on the state of the
ENPGA#, ENPGB#, and ENPGC# inputs. If the ENPGx# inputs are tied high, the PG[4:1]# outputs turn on
simultaneously.
Bits
Default R/W
Description
3210
0
When bit 3 is cleared, PG[4:1]# signal sequencing is
0b1 R/W ^{simultaneous.}
1
When bit 3 is set, PG[4:1]# signal sequencing is enabled.
00
When bits 2:1 are set to 0b00, the over/under voltage filter is off.
01
10
0b00
When bits 2:1 are set to 0b01, the over/under voltage delay is
5 ms.
R/W _{When bits 2:1 are set to 0b10, the over/under voltage delay is}
80 ms.
11
When bits 2:1 are set to 0b11, the over/under voltage delay is
160 ms.
0
When bit 0 is cleared, the circuit breaker cycle time is 2.5 sec.
0b0 R/W
1
When bit 0 is set, the circuit breaker cycle time is 5 sec.
Table 5. Register 4 Bitmap
Summit Microelectronics
2050 3.7 10/30/02
33