M36W432T Datasheet, PDF (7/57 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36W432T, M36W432B
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is at V_IL, the
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at V_IH, the Lock-Down is disabled and the block
can be locked or unlocked. (refer to Table 6, Read
Protection Register and Protection Register Lock).
Flash Reset (RPF). The Reset input provides a
hardware reset of the Flash memory. When Reset
is at V_IL, the memory is in reset mode: the outputs
are high impedance and the current consumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at V_IH, the device is
in normal operation. Exiting reset mode the device
enters read array mode, but a negative transition
of Chip Enable or a change of the address is re-
quired to ensure valid data outputs.
SRAM Chip Enable (E1S, E2S). The Chip En-
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1S at V_IH or
E2S at V_IL deselects the memory and reduces the
power consumption to the standby level. E1S and
E2S can also be used to control writing to the
SRAM memory array, while WS remains at V_IL. It
is not allowed to set EF at V_IL, E1S at V_IL and E2S
at V_IH at the same time.
SRAM Write Enable (WS). The Write Enable in-
put controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM memory. GS is ac-
tive low.
SRAM Upper Byte Enable (UBS). The Upper
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UBS is active low.
SRAM Lower Byte Enable (LBS). The Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LBS is active low.
V_DDF Supply Voltage (2.7V to 3.3V). V_DDF pro-
vides the power supply to the internal core of the
Flash Memory device. It is the main power supply
for all operations (Read, Program and Erase).
V_DDQF and V_DDS Supply Voltage (2.7V to 3.3V).
V_DDQF provides the power supply for the Flash
memory I/O pins and V_DDS provides the power
supply for the SRAM control pins. This allows all
Outputs to be powered independently from the
Flash core power supply, V_DDF. V_DDQF can be tied
to V_DDS
V_PPF Program Supply Voltage. V_PPF is both a
control input and a power supply pin for the Flash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Volt-
age V_DDF and the Program Supply Voltage V_PPF
can be applied in any order.
If V_PPF is kept in a low voltage range (0V to 3.6V)
V_PPF is seen as a control input. In this case a volt-
age lower than V_PPLK gives an absolute protection
against program or erase, while V_PPF > V_PPLK en-
ables these functions (see Table 14, DC Charac-
teristics for the relevant values). V_PPF is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase op-
erations continue.
If V_PPF is in the range 11.4V to 12.6V it acts as a
power supply pin. In this condition V_PPF must be
stable until the Program/Erase algorithm is com-
pleted (see Table 16 and 17).
V_SSF and V_SSS Ground. V_SSF and V_SSS are the
ground reference for all voltage measurements in
the Flash and SRAM chips, respectively.
Note: Each device in a system should have V_D-
DF^{, V}DDQF ^{and V}PPF ^{decoupled with a 0.1µF ca-}
pacitor close to the pin. See Figure 9, AC
Measurement Load Circuit. The PCB trace
widths should be sufficient to carry the re-
quired V_PPF program and erase currents.
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