M36W432T Datasheet, PDF (6/57 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36W432T, M36W432B
Figure 3. LFBGA Connections (Top view through package)
#1
#2
1
2
3
4
5
6
7
8
#3
#4
A
NC
NC
A20
A11
A15
A14
A13
A12 VSSF VDDQF NC
NC
B
A16
A8
A10
A9 DQ15 WS DQ14 DQ7
C
WF
NC
DQ13 DQ6 DQ4 DQ5
D
VSSS RPF
DQ12 E2S VDDS VDDF
E
WPF VPPF A19 DQ11
DQ10 DQ2 DQ3
F
LBS UBS GS
DQ9 DQ8 DQ0 DQ1
G
A18 A17
A7
A6
A3
A2
A1
E1S
H
NC
NC
NC
A5
A4
A0
EF VSSF GF
NC
NC
NC
AI05201
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A17). Addresses A0-A17
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they con-
trol the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (EF) and Write
Enable (WF) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (WS).
Address Inputs (A18-A20). Addresses A18-A20
are inputs for the Flash component only. The
Flash memory is accessed through the Chip En-
able (EF) and Write Enable (WF) signals
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Flash Chip Enable (EF). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at V_IL and Reset is at V_IH the device
is in active mode. When Chip Enable is at V_IH the
memory is deselected, the outputs are high imped-
ance and the power consumption is reduced to the
standby level.
Flash Output Enable (GF). The Output Enable
controls the data outputs during the Bus Read op-
eration of the Flash memory.
Flash Write Enable (WF). The Write Enable
controls the Bus Write operation of the Flash
memory’s Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable, EF, or Write Enable, WF, whichever oc-
curs first.
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