M36W432T Datasheet, PDF (21/57 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36W432T, M36W432B
Write. Write operations are used to write data to
the SRAM. The SRAM is in Write mode whenever
WS and E1S are at V_IL, and E2S is at V_IH. Either
the Chip Enable inputs, E1S and E2S, or the Write
Enable input, WS, must be deasserted during ad-
dress transitions for subsequent write cycles.
A Write operation is initiated when E1S is at V_IL,
E2S is at V_IH and WS is at V_IL. The data is latched
on the falling edge of E1S, the rising edge of E2S
or the falling edge of WS, whichever occurs last.
The Write cycle is terminated on the rising edge of
E1S, the rising edge of WS or the falling edge of
E2S, whichever occurs first.
If the Output is enabled (E1S=V_IL, E2S=V_IH and
GS=V_IL), then WS will return the outputs to high
impedance within t_WLQZ of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. The Data input must be valid for t_D-
VWH ^{before the rising edge of Write Enable, for}
t_DVE1H before the rising edge of E1S or for t_DVE2L
before the falling edge of E2S, whichever occurs
first, and remain valid for t_WHDX, t_E1HAX or t_E2LAX
(see Table 20, Figure 16, 17, 18 and 19).
Standby/Power-Down. The SRAM component
has a chip enabled power-down feature which in-
vokes an automatic standby mode (see Table 19,
Figure 15). The SRAM is in Standby mode when-
ever either Chip Enable is deasserted, E1S at V_IH
or E2S at V_IL.
Data Retention. The SRAM data retention per-
formances as V_DDS goes down to V_DR are de-
scribed in Table 21 and Figure 20, 21. In E1S
controlled data retention mode, the minimum
standby current mode is entered when
E1S ≥ V_DDS – 0.2V and E2S ≤ 0.2V or
E2S ≥ V_DDS – 0.2V. In E2S controlled data reten-
tion mode, minimum standby current mode is en-
tered when E2S ≤ 0.2V.
Output Disable. The data outputs are high im-
pedance when the Output Enable, GS, is at V_IH
with Write Enable, WS, at V_IH.
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
Table 11. Absolute Maximum Ratings
Symbol
Parameter
T_A
Ambient Operating Temperature ⁽¹⁾
T_BIAS
Temperature Under Bias
T_STG
Storage Temperature
V_IO
Input or Output Voltage
V_DDF, V_DDQF Flash Supply Voltage
V_PPF
Program Voltage
V_DDS
SRAM Supply Voltage
Note: 1. Depends on range.
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Min
–40
–40
–55
–0.5
–0.6
–0.6
–0.5
Value
Max
85
125
155
V_DDQF +0.3
3.9
13
3.9
Unit
°C
°C
°C
V
V
V
V
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