M36W432T Datasheet, PDF (20/57 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36W432T, M36W432B
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended. When the Program
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command. The Program Suspend Status
should only be considered valid when the Pro-
gram/Erase Controller Status bit is High (Program/
Erase Controller inactive). Bit 2 is set within 5µs of
the Program/Erase Suspend command being is-
sued therefore the memory may still complete the
operation rather than entering the Suspend mode.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at-
tempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value must be masked.
Note: Refer to Appendix C, Flowcharts and
Pseudo Codes, for using the Status Register.
Table 10. Status Register Bits
Bit
Name
7
P/E.C. Status
6
Erase Suspend Status
5
Erase Status
4
Program Status
3
V_PPF Status
2
Program Suspend Status
1
Block Protection Status
0
Reserved
Note: Logic level '1' is High, '0' is Low.
Logic Level
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Definition
Ready
Busy
Suspended
In progress or Completed
Erase Error
Erase Success
Program Error
Program Success
V_PPF Invalid, Abort
V_PPF OK
Suspended
In Progress or Completed
Program/Erase on protected block, Abort
No operation to protected blocks
SRAM Operations
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable, WS, is at V_IH, Out-
put Enable, GS, is at V_IL, Chip Enable, E1S, is at
V_IL, Chip Enable, E2S, is at V_IH, and Byte Enables,
UBS and LBS are at V_IL.
Valid data will be available on the output pins after
a time of t_AVQV after the last stable address. If the
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t_E1LQV, t_E2HQV, or t_GLQV) rath-
er than the address. Data out may be indetermi-
nate at t_E1LQX, t_E2HQX and t_GLQX, but data lines
will always be valid at t_AVQV (see Table 19, Figures
13 and 14).
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