M36W432T Datasheet, PDF (47/57 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36W432T, M36W432B
Table 32. Primary Algorithm-Specific Extended Query Table
Offset
P = 35h ⁽¹⁾
Data
Description
(P+0)h = 35h 0050h
(P+1)h = 36h 0052h Primary Algorithm extended Query table unique ASCII string “PRI”
(P+2)h = 37h 0049h
(P+3)h = 38h 0031h Major version number, ASCII
(P+4)h = 39h 0030h Minor version number, ASCII
(P+5)h = 3Ah
(P+6)h = 3Bh
(P+7)h = 3Ch
(P+8)h = 3Dh
0066h
0000h
0000h
0000h
Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 31 to 9
Chip Erase supported
Suspend Erase supported
Suspend Program supported
Legacy Lock/Unlock supported
Queued Erase supported
Instant individual block locking supported
Protection bits supported
Page mode read supported
Synchronous read supported
Reserved; undefined bits are ‘0’
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(P+9)h = 3Eh
0001h
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always supported
during Erase or Program operation
bit 0
Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
(P+A)h = 3Fh
(P+B)h = 40h
0003h
0000h
Block Lock Status : Defines which bits in the Block Status Register section of
the Query are implemented.
Address (P+A)h contains less significant byte
bit 0
Block Lock Status bit active
(1 = Yes, 0 = No)
bit 1
Block Lock-Down Status bit active
(1 = Yes, 0 = No)
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
(P+C)h = 41h
0030h
V_DD Logic Supply Optimum Program/Erase voltage (highest performance)
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
(P+D)h = 42h
00C0h
V_PP Supply Optimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
(P+E)h = 43h
0001h Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
(P+F)h = 44h
(P+10)h = 45h
(P+11)h = 46h
(P+12)h = 47h
0080h
0000h
0003h
0003h
Protection Field 1: Protection Description
This field describes user-available. One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device unique
serial numbers. Others are user programmable. Bits 0–15 point to the
Protection register Lock byte, the section’s first byte.
The following bytes are factory pre-programmed and user-programmable.
bit 0 to 7
Lock/bytes JEDEC-plane physical low address
bit 8 to 15
bit 16 to 23
bit 24 to 31
Lock/bytes JEDEC-plane physical high address
"n" such that 2ⁿ = factory pre-programmed bytes
"n" such that 2ⁿ = user programmable bytes
(P+13)h = 48h
Reserved
Note: 1. See Table 29, offset 15 for P pointer definition.
Value
"P"
"R"
"I"
"1"
"0"
No
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
Yes
3V
12V
01
80h
00h
8 Byte
8 Byte
47/57