M36W432T Datasheet, PDF (35/57 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

M36W432T, M36W432B
Table 20. SRAM Write AC Characteristics
Symbol
Alt
Parameter
SRAM
Min
Max
Unit
t_AVAV
t_WC Write Cycle Time
70
ns
t_AVE1L
t_AS ⁽¹⁾ Address Valid to Chip Enable 1 Low
0
ns
t_AVE2H
t_AS ⁽¹⁾ Address Valid to Chip Enable 2 High
0
ns
t_AVWH
t_AW Address Valid to Write Enable High
60
ns
t_AVWL
t_AS ⁽¹⁾ Address Valid to Write Enable Low
0
ns
t_BLWH
t_BW UBS, LBS Valid to End of Write
60
ns
t_DVE1H
t_DW Input Valid to Chip Enable 1 High
30
ns
t_DVE2L
t_DW Input Valid to Chip Enable 2 Low
30
ns
t_DVWH
t_DW Input Valid to Write Enable High
30
ns
t_E1HAX
t_WR ⁽²⁾ Chip Enable 1 High to Address Transition
0
ns
t_E1LWH,
t_E2HWH
t_CW ⁽³⁾ Chip Select to End of Write
60
ns
t_E2LAX
t_WR ⁽²⁾ Chip Enable 2 Low to Address Transition
0
ns
t_GHQZ
t_GHZ Output Enable High to Output Hi-Z
25
ns
t_WHAX
t_WR ⁽²⁾ Write Enable High to Address Transition
0
ns
t_WHDX
t_DH Write Enable High to Input Transition
0
ns
t_WHQX
t_OW Write Enable High to Output Transition
10
ns
t_WLQZ
t_WHZ Write Enable Low to Output Hi-Z
25
ns
t_WLWH
t_WP ⁽⁴⁾ Write Enable Pulse Width
50
ns
Note: 1. t_AS is measured from the address valid to the beginning of write.
2. tWR is measured from the end or write to the address change. tWR applied in case a write ends as E1S or WS going high.
3. t_CW is measured from E1S going low end of write.
4. A Write occurs during the overlap (tWP) of low E1S and low WS. A write begins when E1S goes low and WS goes low with asserting
UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the ear-
liest transition when E1S goes high and WS goes high. The t_WP is measured from the beginning of write to the end of write.
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