M36W432T Datasheet, PDF(13/57 Page) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

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M36W432T Datasheet, PDF (13/57 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

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M36W432T, M36W432B

Read Electronic Signature Command. The

Read Electronic Signature command reads the

Manufacturer and Device Codes and the Block

Locking Status, or the Protection Register.

The Read Electronic Signature command consists

of one write cycle, a subsequent read will output

the Manufacturer Code, the Device Code, the

Block Lock and Lock-Down Status, or the Protec-

tion and Lock Register. See Tables 4, 5 and 6 for

the valid address.

Read CFI Query Command. The Read Query

Command is used to read data from the Common

Flash Interface (CFI) Memory Area, allowing pro-

gramming equipment or applications to automati-

cally match their interface to the characteristics of

the device. One Bus Write cycle is required to is-

sue the Read Query Command. Once the com-

mand is issued subsequent Bus Read operations

read from the Common Flash Interface Memory

Area. See Appendix B, Common Flash Interface,

Tables 28, 29, 30, 31, 32 and 33 for details on the

information contained in the Common Flash Inter-

face memory area.

Block Erase Command. The Block Erase com-

mand can be used to erase a block. It sets all the

bits within the selected block to â1â. All previous

data in the block is lost. If the block is protected

then the Erase operation will abort, the data in the

block will not be changed and the Status Register

will output the error.

Two Bus Write cycles are required to issue the

command.

s The first bus cycle sets up the Erase command.

s The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

Erase aborts if Reset turns to VIL. As data integrity

cannot be guaranteed when the Erase operation is

aborted, the block must be erased again.

During Erase operations the memory will accept

the Read Status Register command and the Pro-

gram/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 7, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See Appendix C, Figure 28, Erase Flowchart and

Pseudo Code, for a suggested flowchart for using

the Erase command.

Program Command. The memory array can be

programmed word-by-word. Two bus write cycles

are required to issue the Program Command.

s The first bus cycle sets up the Program

command.

s The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

During Program operations the memory will ac-

cept the Read Status Register command and the

Program/Erase Suspend command. Typical Pro-

gram times are given in Table 7, Program, Erase

Times and Program/Erase Endurance Cycles.

Programming aborts if Reset goes to VIL. As data

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

See Appendix C, Figure 25, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Double Word Program Command. This feature

is offered to improve the programming throughput,

writing a page of two adjacent words in paral-

lel.The two words must differ only for the address

A0. Programming should not be attempted when

VPPF is not at VPPH. The command can be execut-

ed if VPPF is below VPPH but the result is not guar-

anteed.

Three bus write cycles are necessary to issue the

Double Word Program command.

s The first bus cycle sets up the Double Word

Program Command.

s The second bus cycle latches the Address and

the Data of the first word to be written.

s The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to VIL. As data integrity

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 26, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Clear Status Register Command. The Clear

Status Register command can be used to reset

bits 1, 3, 4 and 5 in the Status Register to â0â. One

bus write cycle is required to issue the Clear Sta-

tus Register command.

The bits in the Status Register do not automatical-

ly return to â0â when a new Program or Erase com-

mand is issued. The error bits in the Status

new Program or Erase command.

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