M36W432T Datasheet, PDF(10/57 Page) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

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M36W432T Datasheet, PDF (10/57 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product

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M36W432T, M36W432B

Flash Memory Component

The Flash Memory is a 32 Mbit (2 Mbit x 16) de-

vice that can be erased electrically at the block

level and programmed in-system on a Word-by-

Word basis. These operations can be performed

using a single low voltage (2.7 to 3.3V) supply

and the VDDQF for device I/0 operation feature the

same voltage range. An optional 12V VPPF power

supply is provided to speed up customer pro-

gramming.

The device features an asymmetrical blocked ar-

chitecture with an array of 71 blocks: 8 Parameter

Blocks of 4 KWord and 63 Main Blocks of 32

KWord. The M36W432T device has the Flash

Memory Parameter Blocks at the top of the mem-

ory address space while the M36W432B device lo-

cates the Parameter Blocks starting from the

bottom. The memory maps are shown in Figure 5,

Block Addresses.

The Flash Memory features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

When VPPF â¤ VPPLK all blocks are protected

against program or erase. All blocks are locked at

Power Up.

Each block can be erased separately. Erase can

be suspended in order to perform either read or

program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each block can be

programmed and erased over 100,000 cycles.

The device includes a 128 bit Protection Register

and a Security Block to increase the protection of

a system design. The Protection Register is divid-

ed into two 64 bit segments, the first one contains

a unique device number written by ST, while the

second one is one-time-programmable by the us-

er. The user programmable segment can be per-

manently protected. The Security Block,

parameter block 0, can be permanently protected

by the user. Figure 6, shows the Flash Security

Block Memory Map.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

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