STE2004S Datasheet, PDF (69/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

STE2004S
Electrical characteristics
Table 28. AC operation
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Serial interface (Figure 75)
F_SCLK
Clock frequency
V_DD1 = 1.7V;
8
T_CYC
Clock cycle SCLK
125
T_PWH1
SCLK pulse width HIGH
60
T_PWL1
SCLK pulse width LOW
60
T_S2
CS setup time
V_DD1 = 1.7V
40
T_H2
CS hold time
V_DD1 = 1.7V
50
T_PWH2
CS minimum high time V_DD1 = 1.7V
50
T_S3
SD/C setup time
30
T_H3
SD/C hold time
30
T_S4
SDIN setup time
30
T_H4
SDIN hold time
40
T_S5
SDOUT access time
T_H5
SDOUT disable time vs.
SCLK
0
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
ns
20
ns
T_H6
SDOUT disable time vs.
CS
1.
F_frame
=
f_--o---s---c-
960
0
20
ns
2. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
3. Trise and Tfall (30%-70%) -10ns
4. C_VLCD is the filtering capacitor on VLCD
5. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V_IL and
V_IH with an input voltage swing of V_SS to V_DD
6. Cb is the capacitive load for each bus line.
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