STE2004S Datasheet, PDF (31/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

STE2004S
4
Bus interfaces
Bus interfaces
To provide the widest flexibility and ease of use the STE2004S features six different
methods for interfacing the host controller. To select the desired interface the SEL1, SEL2
and SEL3 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH
(connect to VDD). All the I/O pins of the unused interfaces must be connected to GND.
All interfaces work while the STE2004S is in power down.
Table 7. Bus interfaces
SEL3
SEL2
0
0
0
0
0
1
0
1
1
0
1
0
SEL1
0
1
0
1
0
1
Interface
I²C
SPI 4 lines 8 bit
SPI 3 lines 8 bit
Serial 3 lines 9 bit
Parallel 8080-series
Parallel 68000-series
Note
Read and write; fast and
high speed mode
Read and write
Read and write
Read and write
Read and write
Read and write
4.1
I²C Interface
The I²C interface is a fully complying I²C bus specification, selectable to work in both Fast
(400kHz Clock) and High Speed Mode (3.4MHz).
This bus is intended for communication between different LCs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL
lines must be connected to a positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
– Data transfer may be initiated only when the bus is not busy.
– During data transfer, the data line must remain stable whenever the clock line is
high. Changes in the data line while the clock line is high are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock
is High, define the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock
signal is High, defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the
data line is stable for the duration of the High period of the clock signal. The data on the line
may be changed during the Low period of the clock signal. There is one clock pulse per bit
of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and the stop conditions is not
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