STE2004S Datasheet, PDF (42/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

Bus interfaces
STE2004S
Figure 48. 68000-series parallel interface protocol in reading mode (several bytes)
CS
D/C
R/W
E
D0
to
D7
Note 1) Data Bus is configured in high impedence mode after evry RD rising edge
2) Always the same data is output on D0-D7
LR0046
4.3.2
8080-series parallel interface
If CS is low after the positive edge of RES, the 8080 parallel interface is ready to receive or
transmit data. While CS pin is high the 8080 parallel interface is kept in reset.
Write mode
Data are latched on WR rising edge.
Read mode
Data is output on the D0-D7 bus on the RD rising edge. The data bus is set in high impedance
mode when RD is set to logic 1.
The I2C address or status byte is output on D0-D7 bus, accordingly to R bit value.
Figure 49. 8080-series parallel bus protocol - one byte transmission
CS
D/C
RD
WR
D0
to
D7
LR0083
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