STE2004S Datasheet, PDF (34/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

Bus interfaces
STE2004S
Reading mode
If the R/W bit is set to logic 1 the chip outputs data immediately after the slave address. If
the D/C bit during the last write access is set to a logic 0, the byte read is the status byte.
Figure 33. Communication protocol
WRITE MODE
DRIVER ACK
DRIVER ACK
DRIVER ACK
DRIVER ACK
DRIVER ACK
SS
S 0 1 1 1 1 A A 0 A 1 DC Control Byte A DATA Byte A 0 DC Control Byte A DATA Byte A P
10
R/W Co
SLAVE ADDRESS
READ MODE
DRIVER ACK
COMMAND WORD
MASTER ACK
Co
LAST
CONTROL BYTE
N> 0 BYTE
MSB........LSB
SS
S0 1 1 1 1AA1A
10
P
SSR
0 1 1 1 1AA /
1 0W
C
o
D
C
0
0
0
H
E
HH
[1][0]
A
R/W
DRIVER
CONTROL BYTE
SLAVE ADDRESS
LR0008
4.2
4.2.1
Serial interfaces
STE2004S can feature three different serial synchronized interfaces with the host controller. It is
possible to select a 3-lines SPI, a 4-lines SPI or 3-line 9 bits serial interface.
4-lines SPI interface
The STE2004S 4-lines serial interface is a bidirectional link between the display driver and the
application supervisor. It consists of four lines: one/two for data signals (SDIN, SOUT), one for
clock signals (SCLK), one for the peripheral enable (CS) and one for mode selection (SD/C).
The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial
peripheral power consumption is zero. While CS pin is high the serial interface is kept in reset.
The STE2004S is always a slave on the bus and receives the communication clock on the SCLK
pin from the master.
Information is exchanged byte-wide. During data transfer, the data line is sampled on the positive
SCLK edge.
SD/C line status indicates whether the byte is a command (SD/C =0) or a data (SD/C =1); SD/C
line is read on the eighth SCLK clock pulse during every byte transfer.
If CS stays low after the last bit of a command/data byte, the serial interface expects the MSB of
the next byte at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all
the internal registers are cleared.
If CS is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SDOUT, the driver I²C slave address or the status byte can be read. The command
sequence to read the I²C slave address or the status byte is shown in Figure 34., Figure 35.,
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