STE2004S Datasheet, PDF (10/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

Circuit description
STE2004S
the master configuration. The only recognized configuration is Vop=0 that forces the charge
pump to be in off state whatever is the value of Vsense_aux.
To synchronize the master and slave timing circuits, the slave driver FR_IN pad must be
connected to master driver FR_OUT pad, and slave driver OSC_IN pad must be connected
to the master driver OSC_OUT Pad (Figure 4.). This connection ensures a synchronization
at both frame level (R0 on the master is driven together with the Slave R0 driver) and at
oscillator level (same frame frequency on the master and on the slave). If the
synchronization at frame level is not required, FR_IN pin must be connected toVDD1 or to
VDD1_aux (Figure 5.).
During the power up procesure, the master device must be forced to exit from power down
before the slave device. To enter into PowerDown mode, the slave device must be forced
into power down state before master device.
Figure 4. Master slave logic connection with frame synchronization
STE2004S
VDD1AUX OSCIN FRIN OSCOUT FROUT
STE2004S
FRIN OSCIN
OSCOUT FROUT
LR0219
Figure 5. Master slave logic connection without frame synchronization
STE2004S
VDD1AUX OSCIN FRIN OSCOUT FROUT
STE2004S
OSCIN
OSCOUT FROUT
VDD1AUX
FRIN
LR0220
3.5
Bias levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are
generated. The ratios among these levels and VLCD, should be selected according to the
MUX ratio (m). They are established according to the following (Figure 6.)
VLCD,
n_-----+-----3_--
n+4
VL _{C D} , ⁿⁿ-----++-----²⁴--
VL
CD,
-----²-------
n+4
VL _{C D} , _n-----¹_+-----4--
VL _{C D} ,VS _S
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