STE2004S Datasheet, PDF (16/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

Circuit description
STE2004S
Figure 10. Automatic data RAM writing sequence with V=0 and data RAM mirrored
format (MX=1)^(a)
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
101 100 99 98
3210
LR0051
Figure 11. Automatic data RAM writing sequence with V=1 and data RAM mirrored
format (MX=1)^(a)
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
101 100 99 98
3210
LR0052
Figure 12. Automatic data RAM writing sequence with X-Y carriage return
(V=0; MX=0)
0123
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
X CARR
98 99 100 101
LR0053
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