STE2004S Datasheet, PDF (38/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

Bus interfaces
Figure 40. 3-lines SPI reading sequence
READING SEQUENCE
STE2004S
Set Co bit =1, D/C Bit =0 R/W Bit =1
SDOUT Buffer become active (Low Impedence)
Source 8 pulses on SCLK and
1
Read the ID-Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
4.2.3
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read.
LR0079
3-lines 9 bits serial interface
The STE2004S 3-lines serial interface is a bidirectional link between the display driver and
the application supervisor.
It consists of three lines: one/two for data signals (SDIN, SDOUT), one for clock signals
(SCLK) and one for peripheral enable (CS).
The serial interface is active only if the CS line is set to a logic 0. When CS line is high the
serial peripheral power consumption is zero. While CS pin is high the serial interface is kept
in reset.
The STE2004S is always a slave on the bus and receives the communication clock on the
SCLK pin from the master.
Information is exchanged word-wide. The word is composed of 9 bits. The first bit is named
SD/C and indicates whether the following byte is a command (SD/C =0) or data byte (SD/C
=1). During data transfer, the data line is sampled on the positive SCLK edge.
If CS stays low after the last bit of a command/data byte, the serial interface expects the
SD/C bit of the next word at the next SCLK positive edge. A reset pulse on RES pin
interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared. If CS is low after the positive edge of RES, the serial interface is ready
to receive data.
Throughout SDOUT, only the driver I²C slave address or the status byte can be read. The
command sequence that the I²C slave address or status byte to be read is shown in Figure
43. and Figure 44.. SDOUT is in high impedance in steady state and during data write.
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