STE2004S Datasheet, PDF (50/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

Instruction set
Table 21. Partial display configuration
PD2 PD1 PD0
Section 1
0
0
0
0
0
0
1
8
0
1
0
8
0
1
1
0
1
0
0
16
1
0
1
8
1
1
0
16
1
1
1
16
Section 2
8 + Icon row
0 + Icon row
8 + Icon row
16 + Icon row
0 + Icon row
16 + Icon row
8 + Icon row
16 + Icon row
Table 22. N-Line inversion
NW3 NW2 NW1 NW0
Description
0-Line inversion
0
0
0
0
(Frame inversion)
0
0
0
1 2-Line inversion
0
0
1
0 3-Line inversion
0
0
1
1 4-Line inversion
:
:
:
::
1
1
1
0 15-Line inversion
1
1
1
1 16-Line inversion
STE2004S
Reset state
000
Reset state
0000
5.1
Reset (RES)
At power-on, all internal registers are configured with the default value. The RAM content is
not defined. A reset pulse on the RES pad (active low) re-initializes the internal registers
content see Table 10. All on-going communication with the host controller is interrupted if a
reset pulse is applied. After the power-on, the software reset instruction can be used to re-
load the reset configuration into the internal registers.
The default configuration is:
– Horizontal addressing (V = 0)
– Multiplexing ratio (M[1:0]=0 - MUX 65)
– Normal instruction set (H[1:0] = 0)
– Frame rate (FR[1:0]=”75Hz”)
– Normal display (MX = MY = 0)
– Power down (PD = 1)
– Display blank (E = D = 0)
– Dual partial display disabled (PE=0)
– Address counter X[6: 0] = 0 and Y[4: 0] = 0
– Temperature coefficient (TC[1: 0] = 0)
– V_OP=0
– Y-CARRIAGE=8
– Bias system (BS[2: 0] = 0)
– X-CARRIAGE=101
A memory blank instruction can be used to clear the DDRAM content.
50/79