STE2004S Datasheet, PDF (40/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

Bus interfaces
Figure 44. 3-lines serial reading sequence
READING SEQUENCE
STE2004S
Write a "00000000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 9 pulses on SCLK and
1
Read the ID Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read.
LR0080
4.3
4.3.1
Parallel interface
The STE2004S selectable parallel interfaces are 68000-series and 8080-series. They are
both an 8-bits bi-directional link between the display driver and the application supervisor.
Both parallel interfaces can be read the I²C driver slave address or the status byte.
68000-series parallel interface
If CS is low after the positive edge of RES, the 68000 parallel interface is ready to receive or
transmit data.
While CS pin is high the 68000 parallel interface is kept in reset.
Write mode
If R/W line is set to 0, data is latched on the E falling edge.
Read mode
When R/W line is set to 1, data is output on the D0-D7 bus on the E rising edge. The data
bus is set in high impedance mode when E is set to logic 0.
The I2C address or status byte is output on D0-D7 bus, according to R bit value.
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