STE2004S Datasheet, PDF (14/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

Circuit description
STE2004S
3.8
Display data RAM
The STE2004S, provides an 102X65 bits static RAM to store display data. This is organized
into 9 (Bank0 to Bank8) banks with 102 bytes. One of these banks can be used for icons.
RAM access is accomplished in either one of the bus interfaces provided (see below).
Allowed addresses are X0 to X101 (Horizontal) and Y0 to Y8 (Vertical).
There are four address mode provided to write to RAM:
● Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on
the left of the memory map. The X pointer is increased after each byte written. After the
last column address (X=X-Carriage), Y address pointer jumps to the following bank and
X restarts from X=0. (Figure 8.)
● Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the
left of the memory map. The Y pointer is increased after each byte written. After the last
Y bank address (Y=Y-Carriage), X address pointer jumps to next column and Y restarts
from Y=0 (Figure 9).
● Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on
the right of the memory map. The X pointer is increased after each byte written. After
the last column address (X=X-Carriage), Y address pointer jumps to the next bank and
X restarts from X=0 (Figure 10.).
● Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the
right of the memory map. The Y pointer is increased after each byte written. After the
last Y bank address (Y=Y-Carriage), the X pointer jumps to next column and Y restarts
from Y=0 (Figure 11.).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always
jumps to the cell with address (X;Y) = (0;0) (Figure 12. Figure 13. Figure 14. Figure 15.).
Data bytes in the memory could have the MSB either on top (D0 = 0, Figure 16.) or on the
bottom (D0=1, Figure 17.).
The STE2004S also allows the normal output address to be altered. The display is mirrored
along the X axis if a logic one MY bit is set. Only the memory read process is altered, the
content is not affected in memory.
When ICON MODE=1 the icon row is not mirrored with MY and is not scrolled.
When ICON MODE=0 the icon row is like an other graphic line and is mirrored and scrolled.
When the partial display mode is disabled, there are three multiplex ratios available (MUX
33, MUX 49 and MUX 65). Only a subset of writable rows are output on row drivers in MUX
33,49 and 65 modes.
When Y-Carriage<MUX/8, if MUX 49 is selected only the first 49 memory rows are
visualized; if MUX 33 selected, only the first 33 memory rows. The unused output row and
column drivers must be left floating.
When Y-Carriage<=MUX/8 the icon bank is located to BANK 8 in MUX 65 Mode, to BANK6
in MUX 49 Mode, and to BANK 4 in MUX 33 Mode.
In MUX 33 and MUX 49 modes and Y-Carriage>MUX/8, only lines 33 and 49 are
visualized.
The lines of DDRAM connected on the output drivers using the scrolling function (Range: 0-
Y-Carriage*8) are selectable. When Y-Carriage>MUX/8 lines, the icon row is moved in
DDRAM to the first row of the bank, corresponding to the Y-CARRIAGE Return value, being
always connected on the same output Driver.
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