STE2004S Datasheet, PDF (67/79 Pages) STMicroelectronics – 102 x 65 single-chip LCD controller/driver

STE2004S
Electrical characteristics
7.3
AC operation
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =25°C;
unless otherwise specified.
Table 28. AC operation
Symbol
Parameter
Test condition
Internal oscillator (Figure 71)
F_OSC
Internal oscillator
frequency
V_DD = 2.8V
F_EXT
F_FRAME
T_w(RES)
External oscillator
frequency
Frame frequency
RES LOW pulse width
Reset pulse rejection
fosc or fext = 72 kHz⁽¹⁾
T_{LOGIC Internal logic reset time}
(RES)
T_VDD VDD1 vs. VDD2 Delay
I²C bus interface (Figure 72)^{(2) (3)}
Fast mode
F_SCL SCL clock frequency
T_SU;STA
Set-up time (repeated)
START condition
High speed mode;
Cb=100pF (max);⁽⁴⁾
V_DD1=2
High speed mode;
Cb=400pF (max)⁽⁴⁾;
V_DD1=2
Fast Mode ⁽⁴⁾;V_DD1=1.7V
Cb = 100pF^{(5) (6)}
T_HD;STA
Hold time (repeated)
START condition
Cb = 100pF^{(5) (6)}
T_LOW
Low period of SCLH
clock
Cb = 100pF^{(5) (6)}
T_HIGH
T_SU;DAT
T_HD;DAT
T_r;CL
T_r;CL1
T_f;CL
High period of SCLH
clock
Cb = 100pF^{(5) (6)}
Data set-up time
Cb = 100pF^{(5) (6)}
Data hold time
Cb = 100pF^{(5) (6)}
Rise time of SCLH signal Cb = 100pF^{(5) (6)}
Rise time of SCLH signal
after a repeated START
condition and aftyer an
acknowledge bit
Cb = 100pF^{(5) (6)}
Fall time of SCLH signal Cb = 100pF^{(5) (6)}
Min.
61
20
5
0
DC
DC
DC
160
160
160
160
60
10
10
10
10
Typ.
72
75
Max.
Unit
83
kHz
100
kHz
Hz
µs
1
µs
5
µs
µs
400
kHz
3.4
MHz
1.7
MHz
400
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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