LSM303C Datasheet, PDF (39/53 Pages) –

LSM303C
Register description
8.15
FIFO_CTRL (2Eh)
FIFO control register (r/w)
Table 48. FIFO_CTRL register
FMODE2 FMODE1 FMODE0 FTH4
FTH3
FTH2
FTH1
FTH0
FMODE [2:0]
FTH [4:0]
Table 49. FIFO_CTRL register description
FIFO mode selection bits. Default 000. For further details refer toTable 50
FIFO threshold. Default: 00000. It is the FIFO depth if the STOP_FTH bit in the
CTRL3 (22h) register is set to ‘1’.
Table 50. FIFO mode selection
FMODE2
0
0
0
FMODE1
0
0
1
FMODE0
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Mode
Bypass mode. FIFO turned off
FIFO mode. Stops collecting data when FIFO is full.
Stream mode. If the FIFO is full, the new sample overwrites
the older one
Stream mode until trigger is deasserted, then FIFO mode
Bypass mode until trigger is deasserted, then Stream mode
Not used
Not used
Bypass mode until trigger is deasserted, then FIFO mode
The FIFO trigger is the interrupt generator 1 event, all related information is available in
Section 8.18: IG_SRC1_A (31h).
8.16
FIFO_SRC (2Fh)
FIFO status control register (r)
Table 51. FIFO_SRC register
FTH
OVR
EMPTY
FSS4
FSS3
FSS2
FSS1
FSS0
FTH
OVR
EMPTY
FSS [4:0]
Table 52. FIFO_SRC register description
FIFO threshold status.
0: FIFO filling is lower than FTH level; 1: FIFO filling is equal or higher than
threshold level
Overrun bit status. 0: FIFO is not completely filled; 1: FIFO is completely filled
FIFO empty bit.
0: FIFO not empty; 1: FIFO empty)
FIFO stored data level
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