LSM303C Datasheet, PDF (34/53 Pages) –

Register description
LSM303C
ODR [2:0] is used to set power mode and ODR selection. All frequencies available are given
in the following table.
ODR2
0
0
0
0
1
1
1
1
Table 25. ODR register setting
ODR1
ODR0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
ODR selection
Power down
10 Hz
50 Hz
100 Hz
200 Hz
400 Hz
800 Hz
N.A.
The BDU bit is used to inhibit the update of the output registers until both upper and lower
register parts are read. In default mode (BDU = ‘0’) the output register values are updated
continuously. When the BDU is activated (BDU = ‘1’), the content of the output registers is
not updated until both MSB and LSB are read which avoids reading values related to
different sample times.
Table 26. Low-pass cutoff frequency in high-resolution mode (HR = 1)
HR
CTRL_REG2_A (DFC [1:0]) LP cutoff freq. [Hz]
1
00
ODR/50
1
01
ODR/100
1
10
ODR/9
1
11
ODR/400
8.5
CTRL_REG2_A (21h)
Accelerometer control register 2 (r/w)
Table 27. CTRL_REG2_A register
-
DFC1
DFC0
HPM1
HPM0
FDS
HPIS2
HPIS1
DFC1 [1:0]
HPM [1:0]
Table 28. CTRL_REG2_A register description
High-pass filter cutoff frequency selection: the bandwidth of the high-pass filter
depends on the selected ODR and on the settings of the DFC [1:0] bits
High-pass filter mode selection. Default value: 00
“00” or “10” = normal mode
“01” = reference signal for filtering
“11” = not available
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