LSM303C Datasheet, PDF (36/53 Pages) –

Register description
LSM303C
BW_SCALE
_ODR
IF_ADD_INC
I2C_DISABLE
SIM
Table 32. CTRL_REG4_A register description
if '0' bandwidth is automatically selected according
BW = 400 Hz when ODR = 800 Hz, 50 Hz, 10 Hz;
BW = 200 Hz when ODR = 400 Hz;
BW = 100 Hz when ODR = 200 Hz;
BW = 50 Hz when ODR = 100 Hz;
if '1' bandwidth is selected according to BW [2:1]
excluding ODR = 50 Hz, 10 Hz, BW = 400 Hz
Register address automatically incremented during a multiple byte access with a
serial interface (I²C or SPI). (0: disable; 1: enable)
Disable I²C interface. Default value 0. (0: I²C enable; 1: I²C disable)
SPI Serial Interface Mode selection. Default value: 0
0 = SPI write-only operations enabled; 1 = SPI read and write operations enabled
8.8
CTRL_REG5_A (24h)
Control register 5 (r/w)
Table 33. CTRL_REG5_A register
DEBUG SOFT_RESET DEC1 DEC0 ST2
ST1 H_LACTIVE
PP_OD
DEBUG
SOFT_RESET
DEC [1:0]
ST [2:1]
H_LACTIVE
PP_OD
Table 34. CTRL_REG5_A register description
Debug stepping action selected. Default value: 0 (0: disable; 1: enable)
Soft reset, it acts as POR when 1, then goes to 0
Decimation of acceleration data on OUT REG and FIFO
00: no decimation
01: update every 2 samples
10: update every 4 samples
11: update every 8 samples
Self-test enable. Default value: 00
(00: self-test disabled; Other: see Table 35)
Interrupt active high, low. Default value: 0
(0: active high; 1: active low)
Push-pull/open-drain selection on interrupt pad. Default value: 0
(0: push-pull; 1: open drain)
Table 35. Self-test mode selection
ST2
ST1
Self-test mode
0
0
Normal mode
0
1
Positive sign self-test
1
0
Negative sign self-test
1
1
Not allowed
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