LSM303AGR Datasheet, PDF(37/68 Page) STMicroelectronics – ultra-low-power 3D accelerometer and 3D magnetometer

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

LSM303AGR Datasheet, PDF (37/68 Pages) STMicroelectronics – ultra-low-power 3D accelerometer and 3D magnetometer

◁

LSM303AGR

Digital interfaces

6.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a high-to-low transition on the data line while the SCL line is held high. After this

has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the master.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the high period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded inside the LSM303AGR behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a slave address is sent, once a

slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the

7 LSb represent the actual register address while the MSB enables address auto increment.

If the MSb of the SUB field is â1â, the SUB (register address) is automatically increased to

allow multiple data read/writes.

The slave address is completed with a Read/Write bit. If the bit was â1â (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is â0â (Write)

the master will transmit to the slave with direction unchanged. Table 23 explains how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Table 19. Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 20. Transfer when master is writing multiple bytes to slave

Master ST SAD + W

SUB

DATA

Slave

SAK

Table 21. Transfer when master is receiving (reading) one byte of data from slave

Master ST SAD + W

SUB

SR SAD + R

NMAK SP

Slave

SAK

SAK DATA

Table 22. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W

SUB

SR SAD+R

MAK

NMAK SP

Slave

SAK

SAK DATA

DAT

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit

DocID027765 Rev 5

37/68

▷