LSM303AGR Datasheet, PDF (36/68 Pages) STMicroelectronics – ultra-low-power 3D accelerometer and 3D magnetometer

Digital interfaces
6
Digital interfaces
LSM303AGR
The registers embedded inside the LSM303AGR may be accessed through both the I²C
and SPI serial interfaces. The latter may be SW-configured to operate in 3-wire interface
mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I²C interface, the
CS line must be tied high (i.e. connected to Vdd_IO).
Table 17. Serial interface pin description
Pin name
Pin description
CS_XL, CS_MAG
SCL
SPC
SDA
SDI
SDO
SPI enable
I²C/SPI mode selection (1: SPI idle mode / I²C communication
enabled; 0: SPI communication mode / I²C disabled)
I²C serial clock (SCL)
SPI serial port clock (SPC)
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
6.1
I²C serial interface
The LSM303AGR I²C is a bus slave. The I²C is employed to write data into registers whose
content can also be read back.
The relevant I²C terminology is given in the table below.
Term
Table 18. I²C terminology
Description
Transmitter
Receiver
Master
Slave
The device which sends data to the bus
The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a
transfer
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through an external pull-
up resistor. When the bus is free, both the lines are high.
The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with the
normal mode.
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