LAN91C96I Datasheet, PDF (92/110 Pages) SMSC Corporation – NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER

Chapter 12 Timing Diagrams
Non-PCI Single-Chip Full Duplex Ethernet Controller
A0-15
AEN, nSBHE
nIOCS16
nIORD
VALID ADDRESS
t15
t4
t3
t20
D0-15
t5
t6
VALID DATA ^Z
OUT
VALID ADDRESS
VALID DATAZ
OUT
Parameter
min
typ
t3 Address, nSBHE, AEN Setup to Control Active 10
t4 Address, nSBHE, AEN Hold after Control
20
Inactive
t5 nIORD Low to Valid Data
t6 nIORD High to Data Floating
t15 A4-A15, AEN Low, BALE High to nIOCS16
Low
t20 Cycle time*
185
max
25
15
12
units
ns
ns
ns
ns
ns
ns
BALE Tied High
IOCHRDY not used - t20 has to be met
*Note: The cycle time is defined only for consecutive accesses to the Data Register. These
values assume
that IOCHRDY is not used.
Figure 12.1 – Local Bus Consecutive Read Cycles
Rev. 11/18/2004
Page 92
DATASHEET
SMSC DS – LAN91C96I