LAN91C96I Datasheet, PDF (28/110 Pages) SMSC Corporation – NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER

Non-PCI Single-Chip Full Duplex Ethernet Controller
5.3
Reset Logic
The pins and bits involved in the different reset mechanisms are:
RESET - Input Pin
SRESET - Soft Reset bit in ECOR, or the SRESET bit
SOFT RST - EPH Soft Reset bit in RCR
RESET pin
ECOR
Register
SRESET bit
SOFT RST
Table 5.4 – Reset Logic
RESETS THE FOLLOWING FUNCTIONS
All internal logic
The Ethernet controller function except for
the bit itself. Setting this bit also lowers
the nIREQ/READY line. When cleared,
the nIREQ/READY line is raised.
The Ethernet controller itself except for
the IA, CONF and BASE registers.
SAMPLES
LOCAL BUS
MODE
Yes
No
No
TRIGGERS
EEPROM
READ
Yes
Yes
No
5.4
Power Down Logic States
Tables Table 5.5 and Table 5.6 describe the power down states of the LAN91C96I. The pins and bits
involved in power down are:
1. PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0).
2. Pwrdwn bits in ECSR
3. Enable Function bit in ECOR
4. PWRDN - Legacy power down bit in Control Register.
Rev. 11/18/2004
Page 28
DATASHEET
SMSC DS – LAN91C96I