LAN91C96I Datasheet, PDF (83/110 Pages) SMSC Corporation – NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER

Non-PCI Single-Chip Full Duplex Ethernet Controller
Note:
On EEPROM read operations (after setting RELOAD high) the EEPROM word address defined by the
POINTER REGISTER 6 least significant bits is read into the GENERAL PURPOSE REGISTER.
On EEPROM write operations (after setting the STORE bit) the value of the GENERAL PURPOSE
REGISTER is written at the EEPROM word address defined by the POINTER REGISTER 6 least
significant bits.
RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the
value until read low is used to determine completion. When an EEPROM access is in progress the
STORE and RELOAD bits of CTR will read-back as both bits high. No other bits of the LAN91C96I
can be read or written until the EEPROM operation completes and both bits are clear. This
mechanism is also valid for reset initiated reloads.
If no EEPROM is connected to the LAN91C96I, the ENEEP pin should be grounded and no accesses to
the EEPROM will be attempted. Configuration, Base and Individual Addresses assume their default values
upon hardware reset and the CPU is responsible for programming them for their final value.
10.1 Diagnostic LEDs
The following LED drive signals are available for diagnostic and installation aid purposes:
ƒ nTXLED - Activated by transmit activity.
ƒ nBSELED - Board select LED. Activated when the board space is accessed, namely on accesses to
the LAN91C96I register space or the ROM area decoded by the LAN91C96I. The signal is stretched
to 125 msec.
ƒ nRXLED - Activated by receive activity.
ƒ nLINKLED - Reflects the link integrity status.
10.2 Bus Clock Considerations
The arbiter exploits the sequential nature of the CPU accesses to provide a very fast access time.
Memory bandwidth considerations will have an effect on the CPU cycle time but no effect on access time.
For normal 8MHz, 10MHz, and 12.5MHz Local Bus, as well as EISA normal cycles, the LAN91C96I can
be accessed without negating ready.
See Arbitration Considerations in Functional Description of the Blocks for more details.
SMSC DS – LAN91C96I
Page 83
DATASHEET
Rev. 11/18/2004