LAN91C96I Datasheet, PDF (34/110 Pages) SMSC Corporation – NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER

Non-PCI Single-Chip Full Duplex Ethernet Controller
7.1
I/O Space Access
The address is determined by the Ethernet I/O Base Registers. The Ethernet I/O space can be configured
as an 8 or 16 bit I/O space, and is similar to the LAN91C94, LAN91C92, etc. I/O space mapping. To limit
the I/O space requirements to 16 locations, the registers are Split into 4 banks in Local Bus mode. The last
word of the I/O area is shared by all banks and can be used to change the bank in use. Banks 0 through 3
functionally correspond to the LAN91C94 banks.
Registers are described using the following convention:
OFFSET
E
NAME
BANK SELECT
REGISTER
TYPE
READ/WRITE
SYMBOL
BSR
BIT 15
RST
Val
BIT 7
RST
Val
BIT14
RST
Val
BIT 6
RST
Val
BIT 13
RST
Val
BIT 5
RST
Val
BIT 12
RST
Val
BIT 4
RST
Val
BIT 11
RST
Val
BIT 3
RST
Val
BIT 10
RST
Val
BIT 2
RST
Val
BIT9
RST
Val
BIT 1
RST
Val
BIT8
RST
Val
BIT 0
RST
Val
OFFSET - Defines the address offset within the IOBASE where the register can be accessed at, provided
the bank select has the appropriate value. The offset specifies the address of the even byte (bits 0-7) or
the address of the complete word. The odd byte can be accessed using address (offset + 1).
Some registers (e.g. the Interrupt Ack. or the Interrupt Mask) are functionally described as two eight bit
registers. In such case, the offset of each one is independently specified.
Regardless of the functional description, when the LAN91C96I is in 16 bit mode, all registers can be
accessed as words or bytes.
RST Val - The default bit values upon hard reset are highlighted below each register.
Rev. 11/18/2004
Page 34
DATASHEET
SMSC DS – LAN91C96I