LAN91C96I Datasheet, PDF (20/110 Pages) SMSC Corporation – NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER

Non-PCI Single-Chip Full Duplex Ethernet Controller
Chapter 5 Functional Description
The LAN91C96I includes an arbitrated-shared memory of 6144 bytes. Any portion of this memory can be
used for receive or transmit packets.
The MMU unit allocates RAM memory to be used for transmit and receive packets, using 256 byte pages.
The arbitration is transparent to the CPU in every sense. There is no speed penalty for Local Bus type of
machines due to arbitration. There are no restrictions on what locations can be accessed at any time.
RAM accesses as well as MMU requests are arbitrated.
The RAM is accessed by mapping it into I/O space for sequential access. Except for the RAM accesses
and the MMU request/release commands, I/O accesses are not arbitrated.
The I/O space is 16 bits wide. Provisions for 8 bit systems are handled by the bus interface.
In the system memory space, up to 64 kbytes are decoded by the LAN91C96I as expansion ROM. The
ROM expansion area is 8 bits wide.
Device configuration is done using a serial EEPROM, with support for modifications to the EEPROM at
installation time.
The CSMA/CD core implements the 802.3 MAC layer protocol. It has two independent interfaces, the data
path and the control path.
In Local Bus mode, serial EEPROM is used for configuration and IEEE Node address making it software
compatible to the LAN9xxx family of Ethernet LAN Controllers. The EEPROM is optional for Local Bus
requiring a Minimum size of 64 X 16 bit word addresses.
Both interfaces are 16 bits wide. The control path provides a set of registers used to configure and control
the block. These registers are accessible by the CPU through the LAN91C96I I/O space. The data path is
of sequential access nature and typically works in one direction at any given time. An internal DMA type of
interface connects the data path to the device RAM through the arbiter and MMU.
The CSMA/CD data path interface is not accessible to the host CPU.
The internal DMA interface can arbitrate for RAM access and request memory from the MMU when
necessary.
An encoder/decoder block interfaces the CSMA/CD block on the serial side. The encoder will do the
Manchester encoding of the transmit data at 10 Mb/s, while the decoder will recover the receive clock, and
decode received data.
Carrier and Collision detection signals are also handled by this block and relayed to the CSMA/CD block.
The encoder/decoder block can interface the network through the AUI interface pairs, or it can be
programmed to use the internal 10BASE-T transceiver and connect to a twisted pair network.
The twisted pair interface takes care of the medium dependent signaling for 10BASE-T type of networks.
It is responsible for line interface (with external pulse transformers and pre-distortion resistors), collision
detection as well as the link integrity test function.
The LAN91C96I provides a 16-bit data path into RAM. The RAM is private and can only be accessed by
the system via the arbiter. RAM memory is managed by the MMU. Byte and word accesses to the RAM
are supported.
Rev. 11/18/2004
Page 20
DATASHEET
SMSC DS – LAN91C96I