LAN91C96I Datasheet, PDF (52/110 Pages) SMSC Corporation – NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER

Non-PCI Single-Chip Full Duplex Ethernet Controller
This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C96I
regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory,
and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte
can be accessed through the Data Low or Data High registers. The order to and from the FIFO is
preserved. Byte and word accesses can be mixed on the fly in any order.
This register is mapped into two consecutive word locations to facilitate the usage of double word move
instructions. The DATA register is accessible at any address in the 8 through Ah range, while the number
of bytes being transferred are determined by A0 and nSBHE in local Bus mode.
I/O SPACE - BANK2
OFFSET
C
NAME
INTERRUPT STATUS REGISTER
TYPE
READ ONLY
SYMBOL
IST
TX IDLE
INT
0
ERCV
INT
0
EPH
INT
0
RX_
OVRN
INT
0
ALLOC
INT
0
OFFSET
C
NAME
INTERRUPT ACKNOWLEDGE
REGISTER
TX
EMPTY
INT
1
TX INT RCV INT
0
0
TYPE
WRITE ONLY
SYMBOL
ACK
ERCV
INT
RX_
OVRN
INT
TX
EMPTY
INT
TX INT
OFFSET
D
NAME
INTERRUPT MASK REGISTER
TYPE
READ/WRITE
SYMBOL
MSK
TX IDLE
INT
MASK
0
ERCV
INT
MASK
0
EPH
INT
MASK
0
RX_
OVRN
INT
MASK
0
ALLOC
INT
MASK
0
TX
EMPTY
INT
MASK
0
TX INT
MASK
RCV INT
MASK
0
0
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A
MASK bit being set will cause a hardware interrupt.
TX IDLE INT - Transmit Idle interrupt. Set when the transmit state machine is not active. This bit is used
under the condition where the TX FIFO is still NOT empty, the transmitter is disabled and the host wants to
determine when the transmitter is completed with the current transmit packet. This event usually happens
when the host wants to insert at the head of the transmit queue a frame for example.
Typical flow of events/Condition:
1. The transmit FIFO is not empty
2. The transmit DONE FIFO is either empty or not empty
Rev. 11/18/2004
Page 52
DATASHEET
SMSC DS – LAN91C96I