LAN91C96I Datasheet, PDF (27/110 Pages) SMSC Corporation – NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER

Non-PCI Single-Chip Full Duplex Ethernet Controller
Ethernet I/O
space (1)
Table 5.1 - LAN91C96I Address Space
SIGNALS
USED
nIORD/
nIOWR
LOCAL
BUS
Y
ON-CHIP
DEPTH
Y
16 locations
WIDTH
8 or 16
bits
8 BIT MODE
((nEN16=1)
(16BIT=0))
16 BIT MODE
otherwise
Table 5.2 - Bus Transactions In Local Bus Mode
A0
NSBHE
0
X
D0-7
Even byte
1
X
Odd byte
0
0
Even byte
D8-15
-
-
Odd byte
0
1
Even byte
-
1
0
-
Odd byte
1
1
Invalid cycle
16BIT:
IOis8:
nEN16:
8 Bit mode:
CONFIGURATION REGISTER bit 7
CSR register bit 5
pin nEN16
((IOis8 = 1) + (nMIS16 = 1)
5.2
Interrupt Structure
The Ethernet interrupt is conceptually equivalent to the LAN91C94 interrupt line, it is the or function of all
enabled interrupts within the Ethernet core. The enabling, reporting, and clearing of these sources is
controlled by the ECOR register. The interrupt structure is similar for Local Bus modes with the following
exceptions:
FUNCTION
Interrupt Output
Ethernet Interrupt Source
Ethernet Interrupt Enable
Ethernet Interrupt Status Bit
Table 5.3 – Interrupt Merging
LOCAL BUS MODE
INTR0-3
OR function of all interrupt bits specified in the Interrupt Status Register
ANDed with their respective Enable bits
Not Applicable in Local Bus mode
Intr bit in ECSR
SMSC DS – LAN91C96I
Page 27
DATASHEET
Rev. 11/18/2004