LAN91C96I Datasheet, PDF(43/110 Page) SMSC Corporation – NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER

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LAN91C96I Datasheet, PDF (43/110 Pages) SMSC Corporation – NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER

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Non-PCI Single-Chip Full Duplex Ethernet Controller

INT SEL1-0 - In Local Bus mode, used to select one out of four interrupt pins. The three unused interrupts

are tristated.

INT SEL1

INT SEL0

INTERRUPT PIN USED

INTR0

INTR1

INTR2

INTR3

I/O SPACE - BANK1

OFFSET

NAME

BASE ADDRESS REGISTER

TYPE

READ/WRITE

SYMBOL

BAR

For Local Bus mode only, this register holds the I/O address decode option chosen for the I/O and ROM

space. It is part of the EEPROM saved setup, and is not usually modified during run-time.

A15

A14

ROM SIZE

A13

RA18

RA17

RA16

RA15

RA14

A15 - A13 and A9 - A5 - These bits are compared in Local Bus mode against the I/O address on the bus to

determine the IOBASE for LAN91C96I registers. The 64k I/O space is fully decoded by the LAN91C96I

down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all

zeros.

ROM SIZE - Determines the ROM decode area in Local Bus mode memory space as follows:

00 = ROM disable

01 = 16k: RA14-18 define ROM select.

10 = 32k: RA15-18 define ROM select.

11 = 64k: RA16-18 define ROM select.

RA18-RA14 - These bits are compared in Local Bus mode against the memory address on the bus to

determine if the ROM is being accessed, as a function of the ROM SIZE. ROM accesses are read only

memory accesses defined by MEMRD* going low.

For a full decode of the address space unspecified upper address lines have to be: A19 = "1", A20-A23

lines are not directly decoded, however Local Bus systems will only activate SMEMRD* only when A20-

A23=0.

All bits in this register are loaded from the serial EEPROM in Local Bus Mode only.

The I/O base decode defaults to 300h (namely, the high byte defaults to 18h). ROM SIZE defaults to 01.

ROM decode defaults to CC000 (namely the low byte defaults to 67h).

Below chart shows the decoding of I/O Base Address 300h:

SMSC DS â LAN91C96I

Page 43

DATASHEET

Rev. 11/18/2004

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