COM20019I_0610 Datasheet, PDF (9/70 Pages) SMSC Corporation – Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Chapter 3 Description of Pin Functions
PIN NO
PLCC TQFP
1, 2, 44, 45,
3
46
4, 5, 6,
8, 9,
10, 11,
12
1, 2, 4,
7, 9, 10,
12, 13
26
37
27
39
23
31
24
34
25
36
-
26
NAME
Address
0-2
Data 0-7
nWrite/
Direction
nRead/
nData
Strobe
nReset In
nInterrupt
nChip
Select
Read/Write
Bus Timing
Select
SYMBOL
A0/nMUX
A1
A2/ALE
AD0-AD2,
D3-D7
nWR/DIR
nRD/nDS
nRESET
nINTR
nCS
I/O
DESCRIPTION
MICROCONTROLLER INTERFACE
IN On a non-multiplexed mode, A0-A2 are address
IN
input bits. (A0 is the LSB) On a multiplexed
address/data bus, nMUX tied Low, A1 is left open,
and ALE is tied to the Address Latch Enable signal.
IN A1 is connected to an internal pull-up resistor.
I/O On a non-multiplexed bus, these signals are used
as the lower byte data bus lines. On a multiplexed
address/data bus, AD0-AD2 act as the address
lines (latched by ALE) and as the low data lines.
D3-D7 are always used for data only. These signals
are connected to internal pull-up resistors.
IN nWR is for 80xx CPU, nWR is Write signal input.
Active Low.
DIR is for 68xx CPU, DIR is Bus Direction signal
input. (Low: Write, High: Read.)
IN nRD is for 80xx CPU, nRD is Read signal input.
Active Low.
nDS is for 68xx CPU, nDS is Data Strobe signal
input. Active Low.
IN Hardware reset signal. Active Low.
OUT Interrupt signal output. Active Low.
IN Chip Select input. Active Low.
BUSTMG
IN Read and Write Bus Access Timing mode selecting
signal. Status of this signal effects CPU Timing.
L: High speed timing mode (only for non-
multiplexed bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.
NOTE:
BUSTMG pin does not exist in PLCC package.
SMSC COM20019I 3.3V Rev.C
Page 9
DATASHEET
Rev. 10-31-06