COM20019I_0610 Datasheet, PDF (3/70 Pages) SMSC Corporation – Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
TABLE OF CONTENTS
Chapter 1 General Description ............................................................................................................. 6
Chapter 2 Pin Configurations ............................................................................................................... 7
Chapter 3 Description of Pin Functions ............................................................................................... 9
Chapter 4 Protocol Description........................................................................................................... 12
4.1 NETWORK PROTOCOL................................................................................................................ 12
4.2 DATA RATES................................................................................................................................. 12
4.3 NETWORK RECONFIGURATION ................................................................................................ 12
4.4 BROADCAST MESSAGES............................................................................................................ 13
4.5 EXTENDED TIMEOUT FUNCTION............................................................................................... 13
4.5.1 Response Time.......................................................................................................................................13
4.5.2 Idle Time.................................................................................................................................................13
4.5.3 Reconfiguration Time..............................................................................................................................14
4.6 LINE PROTOCOL .......................................................................................................................... 14
4.6.1 Invitations To Transmit ...........................................................................................................................14
4.6.2 Free Buffer Enquiries..............................................................................................................................14
4.6.3 Data Packets ..........................................................................................................................................15
4.6.4 Acknowledgements.................................................................................................................................15
4.6.5 Negative Acknowledgements .................................................................................................................15
Chapter 5 System Description............................................................................................................. 16
5.1 MICROCONTROLLER INTERFACE ............................................................................................. 16
5.1.1 High Speed CPU Bus Timing Support ....................................................................................................19
5.2 TRANSMISSION MEDIA INTERFACE.......................................................................................... 21
5.2.1 Backplane Configuration.........................................................................................................................21
5.2.2 Differential Driver Configuration..............................................................................................................22
5.2.3 Programmable TXEN Polarity.................................................................................................................22
Chapter 6 Functional Description....................................................................................................... 25
6.1 MICROSEQUENCER .................................................................................................................... 25
6.2 INTERNAL REGISTERS................................................................................................................ 26
6.2.1 Interrupt Mask Register (IMR) ................................................................................................................26
6.2.2 Data Register..........................................................................................................................................27
6.2.3 Tentative ID Register ..............................................................................................................................27
6.2.4 Node ID Register ....................................................................................................................................27
6.2.5 Next ID Register .....................................................................................................................................27
6.2.6 Status Register .......................................................................................................................................27
6.2.7 Diagnostic Status Register .....................................................................................................................28
6.2.8 Command Register.................................................................................................................................28
6.2.9 Address Pointer Registers ......................................................................................................................28
6.2.10 Configuration Register ........................................................................................................................28
6.2.11 Sub-Address Register .........................................................................................................................28
6.2.12 Setup 1 Register .................................................................................................................................28
6.2.13 Setup 2 Register .................................................................................................................................29
6.3 INTERNAL RAM ............................................................................................................................ 36
6.3.1 Sequential Access Memory ....................................................................................................................36
6.3.2 Access Speed.........................................................................................................................................37
6.4 SOFTWARE INTERFACE .............................................................................................................37
6.4.1 Selecting RAM Page Size.......................................................................................................................37
6.4.2 Transmit Sequence.................................................................................................................................39
6.4.3 Receive Sequence..................................................................................................................................40
6.5 COMMAND CHAINING.................................................................................................................. 41
6.5.1 Transmit Command Chaining .................................................................................................................42
6.5.2 Receive Command Chaining ..................................................................................................................42
6.6 RESET DETAILS ........................................................................................................................... 43
SMSC COM20019I 3.3V Rev.C
Page 3
DATASHEET
Rev. 10-31-06