COM20019I_0610 Datasheet, PDF (20/70 Pages) SMSC Corporation – Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

RAM
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip
Write operations are enabled; BUSTMG = 1, the High Speed CPU Read and Write operations are disabled
if the RBUSTMG bit is 0. If BUSTMG = 1 and RBUSTMG = 1, High Speed CPU Read operations are
enabled (see definition of RBUSTMG bit below).
In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply.
z For 28-Pin PLCC package (BUSTMG is tied to 1 internally)
RBUSTMG BIT
0
1
BUS TIMING MODE
Normal Speed CPU Read and Write
High Speed CPU Read and Normal Speed CPU Write
z For 48-Pin TQFP package
BUSTMG PIN
0
1
1
RBUSTMG BIT
X
0
1
BUS TIMING MODE
High Speed CPU Read and Write
Normal Speed CPU Read and Write
High Speed CPU Read and Normal Speed CPU Write
Rev. 10-31-06
Page 20
DATASHEET
SMSC COM20019I 3.3V Rev.C