COM20019I_0610 Datasheet, PDF (32/70 Pages) SMSC Corporation – Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

RAM
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip
DATA
0000 c101
000r p110
0000 1000
COMMAND
Define
Configuration
Clear Flags
Clear
Receive
Interrupt
DESCRIPTION
This command defines the maximum length of packets that may
be handled by the device. If "c" is a logic "1", the device
handles both long and short packets. If "c" is a logic "0", the
device handles only short packets.
This command resets certain status bits of the COM20019I 3V.
A logic "1" on "p" resets the POR status bit and the EXCNAK
Diagnostic status bit. A logic "1" on "r" resets the RECON
status bit.
This command is used only in the Command Chaining
operation. Please refer to the Command Chaining section for
definition of this command.
BIT
BIT NAME
7
Read Data
6
Auto Increment
5-3 (Reserved)
2-0 Address 10-8
Table 6.6 - Address Pointer High Register
SYMBOL
RDDATA
AUTOINC
A10-A8
DESCRIPTION
This bit tells the COM20019I 3V whether the following
access will be a read or write. A logic "1" prepares the
device for a read, a logic "0" prepares it for a write.
This bit controls whether the address pointer will
increment automatically. A logic "1" on this bit allows
automatic increment of the pointer after each access,
while a logic "0" disables this function. Please refer to the
Sequential Access Memory section for further detail.
These bits are undefined. They must be 0.
These bits hold the upper three address bits which
provide addresses to RAM.
BIT
BIT NAME
7-0 Address 7-0
Table 6.7 - Address Pointer Low Register
SYMBOL
A7-A0
DESCRIPTION
These bits hold the lower 8 address bits which provide the
addresses to RAM.
Rev. 10-31-06
Page 32
DATASHEET
SMSC COM20019I 3.3V Rev.C