COM20019I_0610 Datasheet, PDF (23/70 Pages) SMSC Corporation – Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
A0/nMUX
A1
A2/BALE
ADDRESS
DECODING
CIRCUITRY
AD0-AD2,
D3-D7
2K x 8
RAM
ADDITIONAL
REGISTERS
nINTR
nRESET
STATUS/
COMMAND
REGISTER
RESET
LOGIC
MICRO-
SEQUENCER
AND
WORKING
REGISTERS
TX/RX
LOGIC
nRD/nDS
nWR/DIR
nCS
BUS
ARBITRATION
CIRCUITRY
RECONFIGURATION
TIMER
OSCILLATOR
NODE ID
LOGIC
nPULSE1
nPULSE2
nTXEN
RXIN
XTAL1
XTAL2
Figure 5.5 - INTERNAL BLOCK DIAGRAM
SMSC COM20019I 3.3V
Page 23
DATASHEET
Rev. 10-31-06