COM20019I_0610 Datasheet, PDF (69/70 Pages) SMSC Corporation – Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Chapter 11 Appendix B
ISA Bus
AEN
SA15-SA4
SD7-SD0
LS688x2
nG
12 bit
Comparators
P
Q
I/O Address Seeting (DIP Switches)
P=Q
12
12
LS245
A
16 bit Bus
Transceivers
A
B
8
8
DIR
nG
COM20019
nCS
D7-D0
nIOR
nIOW
SA2-SA0
3
3
IRQm
nRD
nWR
A2-A0
nINTR
nIOCS16
DRQn
nDACK
TC
nREFRESH
RESETDRV
nRESET
Schmitt-Trigger Buffer
Figure 11.1 - EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS
SMSC COM20019I 3.3V
Page 69
DATASHEET
Rev. 10-31-06