COM20019I_0610 Datasheet, PDF (63/70 Pages) SMSC Corporation – Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
XTAL1
4.0V
t1
t2
1.0V
Parameter
t1
Input Clock High Time
t2
Input Clock Low Time
t3
Input Clock Period
t4
Input Clock Frequency*
t5
Frequency Accuracy*
Note*: t4 and t5 are applied to crystal oscillaton.
t3
50% of VDD
min typ max units
20
nS
20
nS
50
100 ^nS
10
20 MHz
-200
200 _ppm
Figure 8.14 - TTL INPUT TIMING ON XTAL1 PIN
t1
nRESET
nINTR
t2
Parameter
min typ
t1
nRESET Pulse Width***
t2
nINTR High to Next nINTR Low EF = 0
EF = 1
5TXTL^*
TDR**/2
4TXTL*
Note*: TXTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 312.5 Kbps, TDR = 3200 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
max units
Figure 8.15 - RESET AND INTERRUPT TIMING
SMSC COM20019I 3.3V
Page 63
DATASHEET
Rev. 10-31-06